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Features
* * * * * * * * * *
3.0V to 5.5V Operating Range Lowest Power in It Class Advanced Low-voltage, Zero-power, Electrically Erasable Programmable Logic Device "Zero" Standby Power (25 A Maximum) (Input Transition Detection) Low-voltage Equivalent of ATF22V10CZ Ideal for Battery Powered Systems CMOS- and TTL-compatible Inputs and Outputs Inputs are 5V Tolerant Latch Feature Hold Inputs to Previous Logic States EE Technology - Reprogrammable - 100% Tested High-reliability CMOS Process - 20-year Data Retention - 10,000 Erase/Write Cycles - 2,000V ESD Protection - 200 mA Latch-up Immunity Commercial and Industrial Temperature Ranges Dual Inline and Surface Mount Standard Pinouts Green Package Options (Pb/Halide-free/RoHS Compliant) Available
*
Highperformance EE PLD ATF22LV10CZ ATF22LV10CQZ
* * *
1. Description
The ATF22LV10CZ/CQZ is a high-performance CMOS (electrically erasable) programmable logic device (PLD) that utilizes Atmel's proven electrically erasable Flash memory technology and provides 25 ns speed with standby current of 25 A maximum. All speed ranges are specified over the 3.0V to 5.5V range for industrial and commercial temperature ranges. The ATF22LV10CZ/CQZ provides a low-voltage and edge-sensing "zero" power CMOS PLD solution with "zero" standby power (5 A typical). The ATF22LV10CZ/CQZ powers down automatically to the zero power mode through Atmel's patented Input Transition Detection (ITD) circuitry when the device is idle. The ATF22LV10CZ/CQZ is capable of operating at supply voltages down to 3.0V. Pin "keeper" circuits on input and output pins hold pins to their previous logic levels when idle, which eliminate static power consumed by pull-up resistors. The "CQZ" combines this low high-frequency ICC of the "Q" design with the "Z" feature. The ATF22LV10CZ/CQZ macrocell incorporates a variable product term architecture. Each output is allocated from 8 to 16 product terms which allows highly complex logic functions to be realized. Two additional product terms are included to provide synchronous reset and asynchronous reset. These additional product terms are common to all 10 registers and are automatically cleared upon power-up. Register Preload simplifies testing. A security fuse prevents unauthorized copying of programmed fuse patterns.
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Figure 1-1.
Block Diagram
2. Pin Configurations
Table 2-1.
Pin Name CLK IN I/O GND VCC
Pin Configurations (All Pinouts Top View)
Function Clock Logic Inputs Bi-directional Buffers Ground (3 to 5.5V) Supply
Figure 2-1.
CLK/IN IN IN IN IN IN IN IN IN IN IN GND
TSSOP
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN
Figure 2-2.
DIP/SOIC
CLK/IN IN IN IN IN IN IN IN IN IN IN GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN
Note:
TSSOP is the smallest package of SPLD offering.
Figure 2-3.
PLCC
IN IN CLK/IN VCC* VCC I/O I/O 4 3 2 1 28 27 26
Note:
For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For superior performance, connect VCC to pin 1 and GND to pins 8, 15, and 22.
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IN IN GND GND* IN I/O I/O
12 13 14 15 16 17 18
IN IN IN GND* IN IN IN
5 6 7 8 9 10 11
25 24 23 22 21 20 19
I/O I/O I/O GND* I/O I/O I/O
ATF22LV10C(Q)Z
3. Absolute Maximum Ratings*
Temperature under Bias .................................. -40C to +85C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on Input Pins with Respect to Ground during Programming .....................................-2.0V to +14.0V(1) Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note:
1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns.
4. DC and AC Operating Conditions
Commercial Operating Temperature (Ambient) VCC Power Supply 0C - 70C 3.0V - 5.5V Industrial -40C - 85C 3.0V - 5.5V
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4.1
DC Characteristics
Parameter Input or I/O Low Leakage Current Input or I/O High Leakage Current Condition(2) 0 VIN VIL (Max) (VCC - 0.2)V VIN VCC CZ-25 Com. Ind. Com. Ind. Com. Ind. Com. Ind. 50.0 55.0 18.0 19.0 3.0 4.0 3.0 4.0 Min Typ Max -10.0 10.0 85.0 90.0 50.0 60.0 25.0 50.0 25.0 50.0 -130.0 -0.5 2.0 VIN = VIH or VIL VCC = Min, IOL = 16 mA VIN = VIH or VIL VCCIO = Min, IOH = -2.0 mA IOH = -100 A 2.4 VCC - 0.2V 0.8 VCC + 0.75 0.5 Units A A mA mA mA mA A A A A mA V V V
Symbol IIL IIH
ICC
Clocked Power Supply Current
VCC = Max Outputs Open, f = 15 MHz
CZ-25 CQZ-30 CQZ-30 CZ-25
ISB
Power Supply Current, Standby
VCC = Max VIN = Max Outputs Open
CZ-25 CQZ-30 CQZ-30
IOS(1) VIL VIH VOL
Output Short Circuit Current Input Low Voltage Input High Voltage Output Low Voltage
VOUT = 0.5V
VOH VOH Note:
Output High Voltage Output High Voltage
V V
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 2. For DC characterization, the test condition of VCC = Max corresponds to 3.6V.
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4.2 AC Waveforms
INPUTS, I/O REG. FEEDBACK SYNCH. PRESET
tS
tH tW tW
CP tP tAW ASYNCH. RESET tCO REGISTERED OUTPUTS tPD COMBINATORIAL OUTPUTS VALID VALID tAP VALID tER VALID tER tEA OUTPUT DISABLED tEA OUTPUT DISABLED VALID VALID tAR
4.3
AC Characteristics(1)
-25 -30 Max 25.0 13.0 2.0 15.0 0 25.0 12.5 33.3 35.7 40.0 3.0 3.0 3.0 15.0 25.0 25.0 15.0 25.0 25.0 25.0 10.0 10.0 10.0 20.0 30.0 30.0 20.0 15.0 Min 10.0 10.0 4.0 18.0 0 30.0 15.0 25.0 30.0 33.3 30.0 30.0 3.0 Max 30.0 15.0 20.0 Units ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns ns ns ns Parameter Input or Feedback to Non-registered Output Clock to Feedback Clock to Output Input or Feedback Setup Time Input Hold Time Clock Period Clock Width External Feedback 1/(tS + tCO) Internal Feedback 1/(tS + tCF) No Feedback 1/(tP) Input to Output Enable Input to Output Disable Input or I/O to Asynchronous Reset of Register Setup Time, Synchronous Preset Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset to Clock Recovery Time 1. See ordering information for valid part numbers. Min 3.0
Symbol tPD tCF tCO tS tH tP tW fMAX tEA tER tAP tSP tAW tAR tSPR Note:
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4.4
4.4.1
Input Test Waveforms
Input Test Waveforms and Measurement Levels
4.4.2
Output Test Loads
Note:
Similar competitors devices are specified with slightly different loads. These load differences may affect output signals' delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible device specification conditions.
4.5
Pin Capacitance
Table 4-1. Pin Capacitance (f = 1 MHz, T = 25C(1))
Typ CIN CI/O Note: 5 6 Max 8 8 Units pF pF Conditions VIN = 0V VOUT = 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
4.6
Power-up Reset
The registers in the ATF22LV10CZ/CQZ are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic and start below 0.7V. 2. The clock must remain stable during TPR. 3. After TPR, all input and feedback setup times must be met before driving the clock pin high.
4.7
Preload of Register Outputs
The ATF22LV10CZ/CQZ's registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file
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with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming.
5. Electronic Signature Word
There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data.
6. Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF22LV10CZ/CQZ fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate.
7. Programming/Erasing
Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware & Software Support for information on software/ programming. Table 7-1.
Parameter TPR VRST
Programming/Erasing
Description Power-up Reset Time Power-up Reset Voltage Typ 600 2.3 Max 1000 2.7 Units ns V
8. Input and I/O Pin Keepers
All ATF22LV10CZ/CQZ family members have internal input and I/O pin-keeper circuits. Therefore, whenever inputs or I/Os are not being driven externally, they will maintain their last driven state. This ensures that all logic array inputs and device outputs are at known states. These are relatively weak active circuits that can be easily overridden by TTL-compatible drivers (see input and I/O diagrams below). Figure 8-1. Input Diagram
VCC
100K
INPUT
ESD PROTECTION CIRCUIT
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Figure 8-2.
I/O Diagram
VCC OE DA A T I/O
VCC
INPUT 100K
9. Functional Logic Diagram Description
The Functional Logic Diagram describes the ATF22LV10CZ/CQZ architecture. The ATF22LV10CZ/CQZ has 12 inputs and 10 I/O macrocells. Each macrocell can be configured into one of four output configurations: active high/low or registered/combinatorial. The universal architecture of the ATF22LV10CZ/CQZ can be programmed to emulate most 24-pin PAL devices. Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF22LV10CZ/CQZ. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the security fuse.
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Figure 9-1. Functional Logic Diagram ATF22LV10CZ/CQZ
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ATF22LV10CZ/CQZ STANDBY CURRENT VS. SUPPLY VOLTAGE (T A = 25C)
NORMALIZED ICC
NORMALIZED I CC VS. TEMP
1.2 1.1 1.0 0.9 0.8 -40.0
3.500 3.000 2.500 2.000 1.500 1.000 0.500 0.000 3.00 ICC (uA)
3.30 VCC (V)
3.60
0.0 25.0 TEMPERATURE (C)
75.0
ATF22LV10CZ SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 3.3V, T A = 25C)
60.000 50.000
ATF22LV10CQZ SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 3.3V, T A = 25C)
25.000 20.000 ICC (mA) 15.000 10.000 5.000 0.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 Frequency (MHz)
40.000 ICC (mA) 30.000 20.000 10.000 0.000 0 0.5 2.5 5 7.5 10 25 37.5 50
Frequency (MHz)
ATF22LV10CZ/CQZ SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V)
0.0 Ioh (mA) -4.0 -6.0 -8.0 -10.0 -12.0 3.0 3.2 3.3 SUPPLY VOLTAGE (V) 3.5 3.6
IOH (mA)
0.0 -2.0 -4.0 -6.0 -8.0 -10.0 -12.0 -14.0 2.0
ATF22LV10C/CZ OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 3.3V, TA = 25C)
-2.0
2.2
2.4
2.6 2.8 VOH (V)
3.0
3.2
3.3
40.0 39.0 38.0 37.0 36.0 35.0 34.0 33.0 32.0 3.0
ATF22LV10CZ/CQZ OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V)
100.0 80.0 IOL (mA) 60.0 40.0 20.0
3.2 3.3 SUPPLY VOLTAGE (V) 3.5 3.6
ATF22LV10CZ/CQZ OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 3.3V, TA = 25C)
IOL (mA)
0.0 0.00
0.50
1.00
1.50 2.00 VOL (V)
2.50
3.00
3.30
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ATF22LV10CZ/CQZ INPUT CLAMP CURRENT VS. INPUT VOLTAGE (VCC = 3.3V, TA = 25C)
INPUT CURRENT (A) INPUT CURRENT (mA) 20.0 0.0 -20.0 -40.0 -60.0 -80.0 -100.0 -120.0 0.0 -0.2 -0.4 -0.6 INPUT VOLTAGE (V) -0.8 -1.0 15.0 10.0 5.0 0.0 -5.0 0.0
ATF22LV10CZ/CQZ INPUT CURRENT VS. INPUT VOLTAGE (VCC = 3.3V, TA = 25C)
0.5
1.0
1.5 2.0 2.5 INPUT VOLTAGE (V)
3.0
3.5
4.0
NORMALIZED TPD VS. VCC
NORMALIZED TPD NORMALIZED TPD 1.2 1.1 1.0 0.9 0.8 3.0 3.2 3.3 SUPPLY VOLTAGE (V) 3.5 3.6 1.2 1.1 1.0 0.9 0.8 -40.0
NORMALIZED TPD VS. TEMP
0.0 25.0 TEMPERATURE (C)
75.0
NORMALIZED TCO VS. VCC
1.2 NORMALIZED TCO 1.1 1.0 0.9 0.8 3.0 3.2 3.3 SUPPLY VOLTAGE (V) 3.5 3.6 NORMALIZED TCO 1.2 1.1 1.0 0.9 0.8 -40.0
NORMALIZED TCO VS. TEMP
0.0
25.0
75.0
TEMPERATURE (C)
NORMALIZED TSU VS. VCC
1.2 NORMALIZED TSU 1.1 1.0 0.9 0.8 3.0 3.2 3.3 SUPPLY VOLTAGE (V) 3.5 3.6 NORMALIZED TSU 1.2 1.1 1.0 0.9 0.8 -40.0
NORMALIZED TSU VS. TEMP
0.0
25.0
75.0
TEMPERATURE (C)
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22LV10CZ/CQZ DELTA TPD VS. OUTPUT LOADING
15.0 DELTA TPD (ns) 10.0 5.0 0.0 -5.0 0.00 DELTA TCO (ns) 15.0 10.0 5.0 0.0 -5.0 0.00
22LV10CZ/CQZ DELTA TCO VS. OUTPUT LOADING
0.50
1.00 1.50 2.00 OUTPUT LOADING (PF)
2.50
3.00
0.50
1.00 1.50 2.00 OUTPUT LOADING (PF)
2.50
3.00
DELTA TPD VS. # OF OUTPUT SWITCHING
DELTA TPD (ns) DELTA TCO (ns) 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 0.0 -0.1 -0.1 -0.2 -0.2 -0.3 1.0
DELTA TCO VS. # OF OUTPUT SWITCHING
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS SWITCHING
NUMBER OF OUTPUTS SWITCHING
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10. Ordering Information
10.1 Standard Package Options
tS (ns) tCO (ns) Ordering Code ATF22LV10CZ-25JC ATF22LV10CZ-25PC ATF22LV10CZ-25SC ATF22LV10CZ-25XC ATF22LV10CZ-25JI ATF22LV10CZ-25PI ATF22LV10CZ-25SI ATF22LV10CZ-25XI ATF22LV10CQZ-30JC ATF22LV10CQZ-30PC ATF22LV10CQZ-30SC ATF22LV10CQZ-30XC ATF22LV10CQZ-30JI ATF22LV10CQZ-30PI ATF22LV10CQZ-30SI ATF22LV10CQZ-30XI Package 28J 24P3 24S 24X 28J 24P3 24S 24X 28J 24P3 24S 24X 28J 24P3 24S 24X Operation Range Commercial (0C to 70C)
tPD (ns)
Industrial (-40C to +85C) Commercial (0C to 70C)
25
15
15
Industrial (-40C to +85C)
10.2
ATF22LV10CQZ Green Package Options (Pb/Halide-free/RoHS Compliant)
tS (ns) tCO (ns) Ordering Code ATF22LV10CQZ-30JU ATF22LV10CQZ-30PU ATF22LV10CQZ-30SU ATF22LV10CQZ-30XU Package 28J 24P3 24S 24X Operating Range Industrial (-40C to +85C)
tPD (ns)
30
15
15
10.3
Using "C" Product for Industrial
To use commercial product for industrial temperature ranges, simply de-rate ICC by 15% on the "C" device. No speed de-rating is necessary.
Package Type 28J 24P3 24S 24X 28-lead, Plastic J-leaded Chip Carrier (PLCC) 24-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) 24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
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11. Packaging Information
11.1 28J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075)
E1 B
E
B1
D2/E2
e D1 D A A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 12.319 11.430 12.319 11.430 9.906 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 12.573 11.582 12.573 11.582 10.922 0.813 0.533 Note 2 Note 2 NOTE
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 28J REV. B
R
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11.2 24P3 - PDIP
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eC eB
SYMBOL A A1 D E E1 B Notes: 1. 2. This package conforms to JEDEC reference MS-001, Variation AF. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB eC e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 31.623 7.620 6.096 0.356 1.270 2.921 0.203 - 0.000 NOM - - - - - - - - - - - MAX 5.334 - 32.131 8.255 7.112 0.559 1.651 3.810 0.356 10.922 1.524 Note 2 Note 2 NOTE
2.540 TYP
6/1/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 24P3, 24-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 24P3 REV. D
R
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11.3
24S - SOIC
B
D1
PIN 1 ID PIN 1
D
e
E A
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN - 0.10 10.00 7.40 15.20 0.33 0.40 0.23 NOM - - - - - - - - 1.27 BSC MAX 2.65 0.30 10.65 7.60 15.60 0.51 1.27 0.32 NOTE
A1
A A1 D D1
0 ~ 8
L1
E B L
L
L1 e
06/17/2002 2325 Orchard Parkway San Jose, CA 95131 TITLE 24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC) DRAWING NO. 24S REV. B
R
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11.4 24X - TSSOP
Dimensions in Millimeter and (Inches)* JEDEC STANDARD MO-153 AD Controlling dimension: millimeters 0.30(0.012) 0.19(0.007)
4.48(0.176) 4.30(0.169)
6.50(0.256) 6.25(0.246)
PIN 1 0.65(0.0256)BSC
7.90(0.311) 7.70(0.303) 1.20(0.047)MAX
0.15(0.006) 0.05(0.002)
0 ~ 8
0.20(0.008) 0.09(0.004) 0.75(0.030) 0.45(0.018)
04/11/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 24X, 24-lead (4.4 mm body width) Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 24X REV. A
R
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12. Revision History
Version No./Release Date Revision L - November 2005 History
1. Added Green Package options
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0779L-PLD-12/05

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